Project Information

• Category: Circuit
• Project Date: February 2019
• Project URL: https://github.com/ChibiKev/Simple-Circuit-Design-and-Testing

Used VHDL and a block diagram to test and run a multiplexer, 3 to 8 decoder, 8 to 3 encoder, 1 bit half adder, and a 1 bit full adder using a 1 bit half adder as a component.

Built circuits and verified the correctness using waveform simulation. Wrote testbench files in VHDL to test the correctness of the design; in addition to using the Quartus Library of Parameterized Modules and comparing the functional performance with the design.